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Sr. Elect Design Verification Engineer

  • 面议

    上海市|工作经验:不限|学历:本科|招聘1人|全职

  • 津贴福利 带薪年假
  • 发布时间:2018-03-28 09:28:08

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职位类别:

IC验证工程师

职位描述:

Job Description:

· Responsible for whole flow of IP verification, including verification requirement generation, test bench coding and coverage closure.

· Develop UVM based IP verification environment and involve in SoC level verification.

· SoC level verification, including subsystem VIP integration, full chip tests coding and regression.

· Power aware verification with UPF.

· SoC gate level verification.

· Promote IP level DFT vector to chip level, run simulation and debug.

· As a key role of verification team, contribute to improve the productivity of the team.

Job Requirements:

· Good knowledge on full cycle of digital verification.

· Good knowledge on System Verilog.

· Experience with EDA tools for digital verification.

· Experience with UVM or OVM is plus.

· Good communication skill, and fluent English.

· Good team player and strong sense of responsibility to deliver on time.

Education & Work Experience:

· MS EE

· NCG or graduated within 1 year from Tier 1 university

公司介绍:

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工作地址:

上海市 - 浦东新区 上海浦东新区张江镇

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